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Commercial/Industrial
PEELTM 22LV10AZ-25 / I-35 CMOS Programmable Electrically Erasable Logic Device
Features
* Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 A (typical) at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-B) - 5 Volt tolerant inputs and I/O's CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Application Versatility - Replaces random logic - Super set of standard PLDs - Pin and JEDEC compatible with 22V10 - Ideal for battery powered systems - Replaces expensive oscillators * * Architectural Flexibility - Enhanced architecture fits in more logic - 133 product terms x 44 input AND array - 12 inputs and 10 I/O pins - 12 possible macrocell configurations - Asynchronous clear, synchronous preset - Independent output enables - Programmable clock; pin 1 or p-term - Programmable clock polarity - 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC - Schmitt triggers on clock and data inputs Schmitt Trigger Inputs - Eliminates external Schmitt trigger devices - Ideal for encoder designs
*
*
General Description
The PEEL22LV10AZ is a Programmable Electrically Erasable Logic (PEEL) SPLD (Simple Programmable Logic Device) that operates over the supply voltage range of 2.7V-3.6V and features ultra-low, automatic "zero" power-down operation. The PEEL22LV10AZ is logically and functionally similar to ICT's 5V PEEL22CV10A and PEEL22CV10AZ. The "zero power" (25 A max. ICC) power-down mode makes the PEEL22LV10AZ ideal for a broad range of batterypowered portable equipment applications, from handheld meters to PCMCIA modems. EEreprogrammability provides both the convenience of product fast reprogramming for product development and quick personalization in manufacturing, including Engineering Change Orders. Figure 1 - Pin Configuration
I/CLK I I I I I I I I I I G ND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/CLK I I I I I I I I I I G ND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
The differences between the PEEL22LV10AZ and PEEL22CV10A include the addition of programmable clock polarity, p-term clock, and Schmitt trigger input buffers on all inputs, including the clock. Schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. Like the PEEL22CV10A, the PEEL22LV10AZ is a pin and JEDEC compatible, logical superset of the industry standard PAL22V10 SPLD Figure 1. The PEEL22LV10AZ provides additional architectural features that allow more logic to be incorporated into the design. The PEEL22LV10AZ architecture allows it to replace over twenty standard 24-pin DIP, SOIC, TSSOP and PLCC packages.
Figure 2 - Block Diagram
CLK MUX (O ptiona l)
I I I NC I I I
4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18
I I I/CLK NC VCC I/O I/O
DIP
TSSOP
I/CLK I I I I I I I I I I I
SP AC PEEL "AND" ARRAY
TM
OE MACRO CEL L I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
133 Terms X 44 Inp uts
I/O I/O I/O NC I/O I/O I/O
I I G ND NC I I/O I/O
I/CLK I I I I I I I I I I G ND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
SP = SYNCHRONO US PRESET AC = ASYNCHRONO US CLEAR O E = O UTPUT ENABLE
PLCC
SOIC
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PEELTM 22LV10AZ
(
132 0
N
ASYNC HRONOUS CLEAR (TO A LL MA C ROCE LLS)
2
9
MACRO CELL
I/O*
(27)
I/CLK*
(2)
10
MACRO CELL
20
I/O*
(26)
I*
(3)
21
MACRO CELL
33
I/O*
(25)
I*
(4)
34
MACRO CELL
48
I/O*
(24)
I*
49
(5)
MACRO CELL
65
I/O*
(23)
I*
(6)
66
MACRO CELL
82
I/O*
(21)
I*
(7)
83
MACRO CELL
97
I/O*
(20)
I*
(9)
98
MACRO CELL
110
I/O*
(19)
I*
(10)
111
MACRO CELL
121
I/O*
(18)
I*
124
(11)
130
MACRO CELL
SYNCHRONO PRESET US (TO A LL MA C ROCE LLS)
I/O*
(17)
I*
(12)
131
I*
(13)
I* * Schmitt Trigger Inputs
(16)
Figure 3 - PEEL22LV10AZ Logic Array Diagram
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PEELTM 22LV10AZ Function Description
The PEEL22LV10AZ implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. ICT has added optional enhanced capabilities to the PEEL22CV10A family of products with additional features and added fuses to support them. Please view the comparison chart found below for the best algorithm Algorithms Number of Fuses Supported Features PEEL V10A Algorithm 5828 Standard 22V10 JEDEC Compatible 4 macrocell options PEEL V10A+ Algorithm 5873 Superset of standard 22V10 12 macrocell options 3 byte signature word Security bit PEEL V10A++ Algorithm 5958 Superset of standard 22V10 (recommended for new designs) 12 macrocell options 8 byte signature word Security bit Clock source selection Clock polarity selection Table 1 - Programming Algorithm Comparison
Architecture Overview The PEEL22LV10AZ architecture is illustrated in the block diagram of Figure 2. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable electrically erasable AND array that drives a fixed OR array. With this structure, the PEEL22LV10AZ can implement up to 10 sum-ofproducts logic expressions. Associated with each of the ten OR functions is an I/O macrocell that can be independently programmed to one of 12 different configurations, including the four standard 22V10 modes. The programmable macrocells allow each I/O to be used to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND array. AND/OR Logic Array The programmable AND array of the PEEL22LV10AZ (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: * 44 Input Lines: - 24 input lines carry the true and complement of the signals applied to the 12 input pins - 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os
* 133 Product Terms: - 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) are used to form sum of product functions - 10 outputs enable terms (one for each I/O) - 1 global synchronous preset term - 1 global asynchronous clear term - 1 programmable clock term At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a "don't care" state exists and that term will always be TRUE. When programming the PEEL22LV10AZ, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function).
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PEELTM 22LV10AZ
Programmable I/O Macrocell The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently lets you to tailor the configuration of the PEEL22LV10AZ to the precise requirements of your design. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell is determined by the four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered or non-registered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1 for details. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 6. In addition to emulating the four PAL-type output structures (configurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. When creating a PEEL device design, the desired macrocell configuration is generally specified explicitly in the design file. When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file. Output Type The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the Dtype flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register is set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear sets Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Output Polarity Each macrocell can be configured to implement activehigh or active-low logic. Programmable polarity eliminates the need for external inverters. Output Enable The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is switched into the high-impedance state. Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bi-directional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically false and the I/O will function as a dedicated input. Input/Feedback Select The PEEL22LV10AZ macrocell also provides control over the feedback path. The input/feedback signal associated with each I/O macrocell can be obtained from three different locations; from the I/O input pin, from the Q output of the flip-flop (registered feedback), or directly from the OR gate (combinatorial feedback). Bi-directional I/O The input/feedback signal is taken from the I/O pin when using the pin as a dedicated input or as a bidirectional I/O. (Note that it is possible to create a registered output function with a bi-directional I/O, refer to Figure 4.
Figure 4 - Block Diagram of the PEEL22LV10AZ I/O Macrocell Combinatorial Feedback The signal-select multiplexer gives the macrocell the ability to feedback the output of the OR gate, bypassing the output buffer, regardless of whether the output function is registered or combinatorial. This feature allows the creation of asynchronous latches, even when the output must be disabled. (Refer to configurations 5, 6, 7, and 8 in Figure 6.) Registered Feedback Feedback also can be taken from the register, regardless of whether the output function is programmed to be combinatorial or registered. When implementing a combinatorial output function, registered feedback allows for the internal latching of states without giving up the use of the external output.
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PEELTM 22LV10AZ
Programmable Clock Options (see Table 1) A unique feature of the PEEL22LV10AZ is a programmable clock multiplexer that allows the user to select true or complement forms of either input pin or product-term clock sources. Operates in both 3 Volt and 3.3 Volt Systems The PEEL22LV10AZ is designed to operate with a VCC range of 2.7 to 3.6 Volts D.C. This allows operation in both 3 Volt 10% (battery operated) and 3.3 Volt 10% (power supply operated) systems. The propagation delay tPD is 5 ns slower at the lower voltage, but this is typically not an issue in battery-operated systems (see Table 6 - A.C. Electrical Characteristics). Zero Power Feature The CMOS PEEL22LV10AZ features "Zero-Power" standby operation for ultra-low power consumption. With the "Zero-Power" feature, transition-detection circuitry monitors the inputs, I/Os (including CLK) and feedbacks. If these signals do not change for a period of time greater than approximately two tPD's, the outputs are latched in their current state and the device automatically powers down. When the next signal transition is detected, the device will "wake up" for active operation until the signals stop switching long enough to trigger the next power-down. (Note that the tPD is approximately 5 ns. slower on the first transition from sleep mode.)
100
As a result of the "Zero-Power" feature, significant power savings can be realized for combinatorial or sequential operations when the inputs or clock change at a modest rate. See Figure 5. When the PEEL22LV10AZ is powered up, a built-in feature holds the outputs in tri-state until VCC reaches 2.2V. This prevents output transitions during power-up. Schmitt Trigger Inputs The PEEL22LV10AZ has Schmitt trigger input buffers on all inputs, including the clock. Schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. They are also useful in cleaning up noisy signals. This makes the PEEL22LV10AZ especially desirable in portable applications where the environment is less predictable. Design Security The PEEL22LV10AZ provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set it is impossible to verify (read) or program the PEEL until the entire device has first been erased with the bulk-erase function. Signature Word The signature word feature allows a 64-bit code to be programmed into the PEEL22LV10AZ if the PEEL V10A+ software option (see Table 1) is used. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. Programming Support ICT's JEDEC file translator allows easy conversion of existing 24 pin PLD designs to the PEEL22LV10AZ, without the need for redesign. ICT supports a broad range of popular third party design entry systems, including Data I/O Synario and Abel, Logical Devices CUPL and others. ICT also offers its proprietary WinPLACE software, an easy-to-use entry level PCbased software development system. Programming support includes all the popular third party programmers; Data I/O, Logical Devices, and numerous others.
10
IC C in mA .
1
0.1
0.01
0.001 0.001
0.01
0.1
1
10
Frequency in MH z
Figure 5 - Typical ICC vs. Input Clock Frequency for the 22LV10AZ
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PEELTM 22LV10AZ
Figure 6 - Twelve Extended I/O Macrocell Configurations (see Table 1)
# 1 2 3 4 5 6 7 8 9 10 11 12
Configuration A B C 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1
D 0 0 0 0 1 1 1 1 0 0 0 0
Input/Feedback Select Register Bi-directional I/O Combinatorial Register Combinatorial Feedback Combinatorial Register Register Feedback Combinatorial
Output Select Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High
Table 2 - Extended Macrocell Configuration Bits (see Table 1)
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PEELTM 22LV10AZ
This device has been designed and tested for the specified operating ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage. Table 3 - Absolute Maximum Ratings Symbol VCC VI, VO IO TST TLT Parameter Supply Voltage Voltage Applied to Any Pin Output Current Storage Temperature Lead Temperature Soldering 10 Seconds
2
Conditions Relative to Ground Relative to Ground Per Pin (IOL, IOH)
1
Rating -0.5 to + 6.0 -0.5 to 5.5 25 -65 to +150 +300
Unit V V mA C C
Table 4 - Operating Range Symbol VCC TA TRVCC Parameter Supply Voltage
3
Conditions Commercial/Industrial Commercial Industrial See Note 4.
Min 2.7 0 -40
Max 3.6 +70 +85 250
Unit V C ms
Ambient Temperature VCC Rise Time
Table 5 - D.C. Electrical Characteristics Over the operating range (unless otherwise specified) Symbol VOH VOHC VOL VOLC VIH VIL VH Parameter Output HIGH Voltage - TTL Output HIGH Voltage - CMOS Output LOW Voltage - TTL Output LOW Voltage - CMOS Input HIGH Voltage Input LOW Voltage Input Voltage Hysteresis Input Leakage Current IIN I/O Leakage Current ICCS ICC
11 8 8
Conditions VCC = Min, IOH = -2.0 mA VCC = Min, IOH = -10 A VCC = Min, IOL = 8.0 mA VCC = Min, IOL = 10 A VCC = 3.3 V VCC = 3.3 V VCC = Max, GND VIN VCC, I/O = High Z VCC = Min, GND VIN 5.5V, I/O = High Z VCC = Max, GND VIN VCC, I/O = High Z VCC = Min, GND VIN 5.5V, I/O = High Z VIN = 0V or VCC, All Outputs disabled VIN = 0V or VCC, All Outputs disabled TA = 25C, VCC = Max @ f = 1 MHz 7
5 5
Min VCC - 0.5 VCC - 0.3
Max
Unit V V
0.4 0.15 2.0 -0.3 0.2 +/- 1 25 +/- 1 500 5 (typ) 1.5 (typ) 25 3 6 12 5.5 0.8
V V V V V A A A A A mA pF pF
VCC Current, Standby VCC Current, f=1MHz Input Capacitance Output Capacitance
CIN
COUT
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PEELTM 22LV10AZ
Table 6 - A.C. Electrical Characteristics 9 (Over the operating range ) -25 Symbol
6
I-35 Units
Parameter Input to non-registered output in continuous 13 mode 6 7 Input to output enable 6 7 Input to output disable Clock to output Clock to comb. Output delay via internal registered feedback Clock to Feedback 6 Input or feedback setup to clock 6 Input hold after clock 9 Clock low time, clock high time Min clock period Ext (tSC + tCO1) 12 Internal feedback 1/ (tSC + tCF) External Feedback (1/ tCP) 12 No Feedback 1/ (tCL + tCH) Asynchronous Reset Pulse Width Input to Asynchronous Reset Asynchronous Reset recovery time 14 Power-on reset time for registers in clear state
Inpu ts I/O , Registered F eedback, Synchronous Preset
3V10% 3.3V10% 3V10% 3.3V10% Min Max Min Max Min Max Min Max
tPD tOE tOD tCO1 tCO2 tCF tSC tHC tCL, tCH tCP fMAX1 fMAX2 fMAX3 tAW tAP tAR tRESET
30 30 30 20 40 14 20 0 20 40 29.4 25 25 30 30 30 5 15 0 13 30 41.6 33.3 38.4 25
25 25 25 15 35 9 28 0 28 56 20.8 17.9 17.9 40 25 25 5
40 40 40 28 56 20 21 0 18 39 29.4 25.6 27.7 35 40 40 5
35 35 35 25 49 13
ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns s
12
35 35 5
Clock Asyn chronou s Rese t Registered O utp uts Combinatoria l O utp uts
Figure 7 - Switching Waveforms Notes:
1. 2. 3. 4. 5. 6. 7. Minimum DC input is -0.5V, however, inputs may undershoot to 2.0V for periods less than 20 ns. VI and VO are not specified for program/verify operation. The Supply Voltage range of 2.7 to 3.6V was chosen to allow this part to be used in both 3V 10% and 3.3V 10% applications. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels. I/O pins are 0V and VCC. "Input" refers to an input pin signal. tOE is measured from input transition to VREF 0.1V, TOD is measured from input transition to VOH -0.1V or VOL +0.1V; VREF =VL Capacitances are tested on a sample basis. 9. Test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5V (Unless otherwise specified). Test one output at a time for duration of less than 1 second. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit Counter. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency. tPD, tOE, tOD, tCO, tSC, and tAP are approximately 5 ns, slower on the first transaction from sleep mode. All inputs at GND.
10. 11. 12.
13. 14.
8.
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PEELTM 22LV10AZ
3.15V Standard Load R1 Output CL R2 Output CL Thevenin Equivalent RL VL
Figure 8 - PEELTM Device and Array Test Loads Technology
CMOS TTL
R1
274k 315
R2
257k 548
RL
110k 200
VL
1.30V 2.00V
CL
33 pF 33 pF
Table 7 - Ordering Information Part Number
PEEL22LV10AZP-25 PEEL22LV10AZPI-35 PEEL22LV10AZJ-25 PEEL22LV10AZJI-35 PEEL22LV10AZS-25 PEEL22LV10AZSI-35 PEEL22LV10AZT-25 PEEL22LV10AZTI-35
Speed
25ns 35ns 25ns 35ns 25ns 35ns 25ns 35ns
Temperature
Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Package
24-pin Plastic DIP 24-pin Plastic DIP 28-pin PLCC 28-pin PLCC 24-pin SOIC 24-pin SOIC 24-pin TSSOP 24-pin TSSOP
Device
Suffix
P E E L TM 22L V 10A Z
PI-35
S p eed P ackag e
-25 = 25ns tpd -35 = 35ns tpd
P = 24-pin Plactic 300 mil DIP J = 24-pin Plastic (J) Leaded Chip Carrier (PLCC) S = 24-pin SOIC 300 mil Gullwing T = 24-pin TSSOP 170 mil
T em p eratu re
(blank) = Commercial 0 to 70 C I = Industrial -40 to 85 C
Figure 9 - Part Number
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PEELTM 22LV10AZ
Corporate Office 2123 Ringwood Avenue San Jose, CA 95131 TEL (408) 434-0678 FAX (408) 432-0815 (c)2001 Integrated Circuit Technology Corp.
Email: sales&marketing@ictpld.com Website: http://www.ictpld.com
ICT reserves the right to make changes in specifications at any time and without notice. The information furnished by ICT in this publication is believed to be accurate and reliable. However, no responsibility is assumed by ICT for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of ICT. ICT's products are not authorized for use as critical components in life support devices or systems. Marks bearing
(c)
or TM are registered trademarks and trademarks of Integrated Circuit Technology Corp.
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